The present invention relates to clock circuits and more particularly to a spread-spectrum phase-locked loop clock generator.
The functioning of a large class of electronic devices is governed by clock signals providing means for timing. Some electronic devices make use of high frequency clock signals, usually generated by multiplying through a frequency synthesizer a reference frequency coming from a high stability crystal-controlled oscillator.
The clock signals are, ideally, rectangular in shape, having energy concentrated at the fundamental frequency and at the integer multiples (harmonics) of this fundamental frequency (as shown in FIG. 1a). In certain situations, the energy of the high frequency harmonics can be large enough to cause disturbance in the functioning of other electronic devices through electromagnetic interference (EMI). The level of accepted electromagnetic interference is regulated by the Federal Communications Commission (FCC).
One way to reduce the amount of electronic interference is to slightly vary the frequency of the clock signal, as to spread the energy of the signal to a larger frequency band. This way, the contribution to electromagnetic interference is reduced at any particular frequency. The slight variation in frequency is usually achieved through frequency or phase modulation. The amount of reduction of the EMI, as well as the deviation of the frequency of the clock signal depend on the amplitude, frequency and shape of the modulation signal. A sketch of a process of spreading the spectrum by slightly down shifting the clock frequency is shown in FIG. 1b. 
One way to spread the spectrum of the clock signal is to modulate the frequency of an oscillator operating in an open-loop mode, as disclosed in U.S. Pat. No. 5,631,920 to Hardin, or U.S. Pat. No. 5,872,807 to Booth et al.
Other approaches are based on a phase-locked loop (PLL) circuit. The phase-locked loop derives its output signal from a voltage-controlled oscillator (VCO). In a conventional PLL, an output signal of the VCO controls a programmable frequency divider, which provides a signal with a lower frequency to one input of a phase detector (PD). The programmable frequency divider divides the VCO output signal through a given integer number. A signal with a reference frequency is applied to another input of the phase detector. The signal with reference frequency comes directly from a reference frequency generator, or is derived, through a frequency divider, either fixed or programmable, from a reference frequency generator. The difference in phase between the divided VCO output and the reference frequency is transformed into a current or voltage, which is filtered by a loop filter (LF) and applied to a control input of the VCO. The loop acts to minimize the difference in phase between the two signals at the input of the frequency detector by changing the output frequency of the VCO. As a result, the frequency of the VCO output is a fractional multiple of the reference frequency. In order to modulate the output frequency of the PLL, a variable modulation signal is applied to a programmable feedback divider.
In order to divide the output frequency by non-integer numbers, the fractional-N technique makes use of rapidly varying the division factor among several integer numbers, selected as to provide over the time an average number equal to the desired non-integer number. See, for instance, the U.S. Pat. No. 4,179,670 Frequency synthesizer with fractional division ratio and jitter compensation, N. G. Kingsbury, Dec. 18, 1978.